SystemVerilog Assertions (SVA) are a powerful mechanism for verifying the correctness of designs. The dist operator is often used to check for sequences of events, but it's possible, and sometimes preferable, to achieve the same results without it. This article explores how to write effective SVA without relying on dist, focusing on clarity, efficiency, and maintainability. We'll also address common scenarios where avoiding dist might be beneficial.
Why Avoid dist?
While dist is a convenient operator for checking for sequences with variable delays, overuse can lead to less readable and less maintainable assertions. Complex dist expressions can be difficult to debug and understand. Furthermore, some simulators might have limitations or inefficiencies when handling complex dist expressions. Therefore, exploring alternative methods can improve code quality and performance.
Alternatives to dist
Several techniques can replace dist in many scenarios:
1. Using always blocks and internal variables
For simple sequence checks, an always block can effectively track events and internal state. This approach is particularly useful when the sequence involves specific timing constraints that aren't easily expressed with dist.
always @(posedge clk) begin
if (event_a) begin
state <= 1;
end else if (state == 1 && event_b) begin
state <= 2;
assert (property (@(posedge clk) state == 2)) else $error("Sequence failed");
end
end
This code checks for the sequence event_a followed by event_b within a single clock cycle. The state variable manages the progression of the sequence.
2. Combining always blocks with sequences
For more complex scenarios, combining always blocks to manage state with separate sequences improves readability. This approach breaks down the assertion logic into smaller, more manageable parts.
sequence seq_1;
event_a ##1 event_b;
endsequence
always @(posedge clk) begin
if (seq_1.triggered) begin
// Action upon successful sequence execution
end
end
Here, seq_1 defines the sequence, and the always block reacts to its completion.
3. Nested sequences
For sequences within sequences, nested sequences provide a structured way to check for complex patterns without relying on dist's ability to handle variable delays directly. The inner sequence defines a sub-pattern, and the outer sequence combines multiple instances or variations of the sub-pattern.
sequence seq_A;
a ##1 b;
endsequence
sequence seq_B;
seq_A ##[1:5] seq_A; // seq_A repeated 2 times with a delay between them of 1 to 5 clock cycles
endsequence
assert property (seq_B);
This example shows seq_A repeated twice with a variable delay in between, avoiding the need for dist in this specific case.
4. Using throughout and until operators
For checking conditions over a period, throughout and until can be more effective than dist. They express temporal relationships clearly.
assert property (@(posedge clk) enable throughout data_valid until done);
This assertion checks that data_valid is true as long as enable is true until done becomes true.
Choosing the Right Approach
The best approach depends on the specific sequence you need to verify. Consider these factors:
- Complexity: For simple sequences,
alwaysblocks might suffice. For more complex sequences, combiningalwaysblocks with sequences or nested sequences improves readability and maintainability. - Timing Constraints: If precise timing is critical, using
alwaysblocks with careful clock cycle accounting provides greater control. - Readability: Prioritize code clarity. If a
dist-based expression becomes overly complex, refactor it using alternative techniques.
By strategically employing these techniques, you can write powerful and efficient SystemVerilog assertions without relying heavily on the dist operator, leading to improved code quality and maintainability. Remember that clear and concise assertions are crucial for effective verification.
